FPGA video image processing algorithm development board camera OV7725 development board VGA LCD output

FPGA video image processing algorithm development board camera OV7725 development board VGA LCD output

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List price:
$ 240.00
Price:
$ 240.00

Product Description

This board is currently mainly suitable for the following categories of people:

(1) on the FPGA logic development has a strong interest, and have a certain basis for the HDL

(2) plans to use FPGA image architecture, learning and research the image algorithm of friends

(3) preparationResearch useFPGA, master FPGA image algorithm to deal with the architecture of a friend

(4) can not find the direction, would like to learn new knowledge, to grasp the future trend of FPGA friends, have the determinationHardshipFriends

VIPFull _Board board introduction:

(1) Full VIP_Board board by CrazyBingo I develop. The Altera Cyclone IV FPGA board, with EP4CE15E17C8N as the core, 24Bit VGA, 24Bit SDRAM, CMOS interface, independent keys, 4*4 matrix keyboard, LCD1602, LED, resource allocation, implementation of video image based on FPGA basic framework, lay the foundation for the late HDL-VIP, can be used as to accelerate video image processing tools VIP algorithm hardware.
(2) for more VIP_Board Full card introduction, logic code, HDL-VIP code routines to achieve analysis, as well as the use of software and other content, please read in detail with reference to the SkyDrive tutorials.

Card routineDesignWill be in this FPGA1.5WindividualLEIn the full use of the peripheral circuit, drainFPGAResources to maximize their speed and performance in order to achieve the most basic video imagesVIPAlgorithm processing function.Exclusive written tutorial: “based on VIP_Board Full FPGA and video portal advanced development guide”,First of all, through the routine to drive, to achieve the external drive circuit, simplifiedFPGA HDL-VIPThe threshold, from the shallower to the deeper gradually lead us into.HDL-VIPRoad of development.

Full VIP_Board on the board of the detailed peripherals and functions, as shown in the following table:

Serial number

functional module

Function introduction

1

FPGA

UseAltera Cyclone IVseriesFPGA,AsVIPTheCPU.EP4CE15F17C8N, with1.5WindividualLEs,166One userIO,

2

VGAModular

UseADV/GM7123Realization24BitTrue colorVGAInterface circuit, as the display interface of the video image

3

SDRAM

Modular

UseHynixThe32Bit SDRAM HY57V283220T, a total of4Banks *1M*32BitResourcesThe interception of the board24Bit), as a video image of the memory

4

CMOSCamera module interface1

Support all series camera module.http://mcudiy.taobao.com),OptionalOV7725/MT9M111etc.CMOSModular.

5

CMOSCamera module interface 2

Support routineFPCInterfaceCMOS Sensor, the default is30WPixelOV7725-FPC.

6

Power module

UseMP2214 DCDCScheme,USBCommunication and power supply, rated fuse500mACurrent, protectionPCFree from harm

7

Part of the crystal

Onboard50MHzAs a crystal oscillator.FPGAClock source.

8

FLASH

UseEPCS4/M25P40serialSPI FLASH,4MbitThe space is enough to bear1W LEs FPGALogic code

9

Key module

(1) 1Global reset button

(2) 4User key

(3) 4*4Matrix keyboard

10

LEDlamp

Onboard8individualLEDLamp, using74HC595Realization3Line serial configuration

11

LCD1602

OnboardLCD1602Circuit, and selection8*5Mini typeLCD1602.

12

DB-40Interface

Lead toVGAMultiplexedDB-40Interface, will support the late withdrawal ofLCDControl panel interface.

13

userIO

extraction35individualCompletely independentuserIO,To provide users with more peripheral expansion program

14

JTAGInterface

standardAltera JTAGInterface, supportsofTest andjicFirmware writing

Board.FPGACode routines, mainly divided intoHDL-LogicAs wellHDL-VIP2Part 1.byHDL-Logi ExamplesThis part of the routine is mainly based onVerilog HDL, the realization of the basic logic of the development of peripheral functions. This part of the main routine is shown in the following table:

Serial number

engineering

describe

1

01_Counter_Design

4Bit counter experiment

2

02-1_LED_Display_Design_8BitAddr

8Bit self plusLEDDisplay experiment (the board can not be tested)

3

02-2_LED_Display_Design_595Addr

Be based on74HC595Serial8BitSince theLEDDisplay experiment

4

02-3_LED_Display_Design_595Water

Be based on74HC595Serial8BitWater lamp display experiment

5

02-4_LED_Display_Design_595Breathe

Be based on74HC595Serial8BitBreathing lamp display experiment

6

03-1_KEY_Scan_Design_Jitter

Implementation of independent key jitter detection based on delay scheme

7

03-2_KEY_Scan_Design_Counter

Implementation of independent key jitter detection based on counting scheme

8

03-3_KEY_Scan_Design_Matrix

Implementation of independent key jitter detection based on counting scheme

9

04_LCD1602_Display_Design

Pure logic implementationLCD1602Display experiment

10

05-1_System_Ctrl_Design

WithoutPLLGlobal clock management module design

11

05-2_System_Ctrl_Design_PLL

beltPLLGlobal clock management module design

13

07_PC2FPGA_UART_Test

Be based onUARTProtocolFPGAandPCSignal communication

14

08-1_VGA_Display_Test_640480

640*480@60Hz VGADriving display experiment

15

08-2_VGA_Display_Test_12801024

1280*1024@60Hz VGADriving display experiment

16

09-1_VGA_Char_Display_Test

Be based onC2MifTheVGACharacter display experiment

17

09-2_SDRAM_VGA_Display_Test640480

Be based onSDRAMTheVGAController design and test

18

10_CMOS_OV7725_RGB640480

Be based onVGATheOV7725 RGBVideo capture and display system

The second part isHDL-VIP ExampleThis part of the routine is mainly based onVerilog HDL, realize based onHDLTheVideo Image ProcessorHardware accelerated processing of video image algorithm. This part of the procedure is shown in the following table:

Serial number

engineering

describe

1

11_VGA_VIP_RGB888_YCbCr444

RGB888turnYCvCr444Realization of algorithm

2

12_VGA_VIP_YCbCr422_RGB888

YCbCrturnRGB888Realization of algorithm

3

13_CMOS_OV7725_Gray_Mean_Filter

Be based onOV7725Average filtering algorithm based on gray level image

4

12_CMOS_OV7725_Gray_Median_Filter

Be based onOV7725Implementation of median filtering algorithm based on gray level image

5

13_CMOS_OV7725_Gray_Median_Sobel

Be based onOV7725Gray level imageSobelEdge detection algorithm

6

16_CMOS_OV7725_Gray_Sobel_Erosion

Gray scale imageSobel+Implementation of corrosion algorithm

7

17_CMOS_OV7725_Gray_Sobel_Erosion_Dilation

Gray scale imageSobel+corrosion+The realization of expansion algorithm

8

11_CMOS_OV7725_RAW8_RGB888

Be based onOV7725TheBayerArray image restoration algorithm

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